1. Field of the Invention
The present invention relates, inter alia, to an image signal processing apparatus for converting an interlace type image signal for displaying an image on a screen of, e.g., a cathode-ray tube into a progressive type image signal for displaying an image on a screen oft e.g., an LCD-TV or a plasma TV.
2. Description of the Related Art
The following description sets forth the inventor's knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art.
In an interlace scanning system, in order to display a single frame image on a screen of e.g., a TV or a display, initially, scanning is performed from the uppermost portion of the screen toward the lowermost portion thereof along odd-numbered scanning lines. Then, returning to the uppermost portion of the screen, scanning is again performed from the uppermost portion toward the lowermost portion thereof along even-numbered scanning lines. Thus, scanning is performed twice for a single frame image. On the other hand, in a progressive scanning system, scanning is completed by a single scanning from the uppermost portion of the screen toward the lowermost portion thereof. In order to display an interlace image, which is a TV image designed for cathode-ray tubes, on a screen of, e.g., an LCD-TV or a plasma TV, interlace-Progressive conversion (hereinafter simply referred to as “IP conversion”) technique for converting an interlace type image signal into a progressive image type signal is required.
Conventionally, for example, such IP conversion has been performed as follows. That is, in the case of an interlace type image signal, in the odd field, since the image signal is inputted only to the odd scanning line, an image signal on either one of the upper and lower scanning lines adjacent to the odd scanning line is inputted into the empty even scanning line. In the same manner, in the even field, since the image signal is inputted only into the even scanning line, an image signal on either one of the upper and lower scanning lines adjacent to the even scanning line is inputted into the empty odd scanning line. Thus, a progressive signal is created.
That is, by simply doubling the scale of the interlace image signal in the vertical direction, it becomes possible to convert the interlace image signal into a progressive image signal. In an interlace image signal, since either the odd scanning lines or even scanning lines are empty, vertically doubling the scale does not cause an increased screen size since either the empty odd scanning lines or the empty even scanning lines are used.
Now, one of scaling methods as a related art will be explained based on a concrete image signal processing circuit having three line memories with reference to FIG. 13. This circuit shown in FIG. 13 includes three line memories 10a, 10b and 10c in the image signal processing circuit. An input data (digital image signal) will be inputted into one of the line memories 10a, 10b and 10c. In this figure, the input data is shown by a single line though it is multiple-bit data. To the line memories 10a, 10b and 10c, a write enable signal is supplied from the memory write control circuit 11. The input data is written in one of the write enabled line memories 10a, 10b and 10c. 
To the memory write control circuit 11, a horizontal synchronizing signal HS1 on the input data, a horizontal data clock signal CK1, and a VSTART signal VATART1 showing the initiation of one frame are supplied. Based on these signals, the memory write control circuit 11 controls the writing of the input data to the line memories 10a, 10b and 10c. 
A memory read/line select control circuit 12 is connected to the line memories 10a, 10b and 10c to control selection of the line memories 10a, 10b and 10c and reading of the selected line memory 10a, 10b or 10c. To the memory read/line select control circuit 12, a horizontal synchronizing signal HS2 on the input data, a horizontal data clock signal CK2, and a scaling ratio set value signal showing the enlarging/reducing ratio are supplied. Also to the memory read/line select control circuit 12, a VSTART signal VSTART2 showing the initiation of reading by the memory read/line select control circuit 12 is supplied from the memory write control circuit 11. The image data read out of the line memories 10a, 10b and 10c will be supplied to the interpolation operation portion 18 via multiplexers MUX 16a and 16b. The interpolation operation portion 18 outputs an image signal required by an output side image signal in accordance with the coefficient of the coefficient generation portion 15.
By using three line memories 10a, 10b and 10c, double scaling in the vertical direction can be performed by outputting one horizontal line data from the line memory and then outputting the same data again. At the time of outputting the same horizontal data, output failure of input data would not cause since the input data is stored using two different line memories. In order to vertically scale, a plurality of line memories will be required since a line memory for outputting data and a line memory for inputting data cannot be shared. As explained above, by double-scaling an interlace image signal, which has half image data as compared with that of a progressive image signal, a progressive image signal can be created (see, e.g. JP 2005-033566, A, JP 2001-109442, A).
In the case of creating a progressive type image signal from an interlace type image signal, in some cases, image processing is performed using two image signals, i.e., a past image signal delayed by one field and a current image signal of a current field. In this case, if the image is in static condition, even if a single image signal is created by simply combining the current and past image signals, there will be no problem. In the case of a moving image, however, in many cases, IP conversion using a motion discrimination circuit is performed in consideration of the motion between the two image signals. If two fields are simply superimposed, in a motion scene, some problems will arise. For example, the image may include horizontal stripes, which is called interlace corn, the image may be recognized as jaggy, and/or the image may deteriorate in sharpness. In order to suppress the aforementioned problems, if complicated detection processing is employed, the entire system will be required to be high in performance. For example, memories will be required every frame. This results in increased cost. On the other hand, in the case of using a cost-effective two-dimensional digital filter, the cost can be kept in relatively low. However, because of the interpolation operation performed in the two-dimensional field, the interpolated image deteriorates in sharpness.
The description herein of advantages and disadvantages of various features, embodiments, methods, and apparatus disclosed in other publications is in no way intended to limit the present invention. For example, certain features of the preferred embodiments of the invention may be capable of overcoming certain disadvantages and/or providing certain advantages, such as, e.g., disadvantages and/or advantages discussed herein, while retaining some or all of the features, embodiments, methods, and apparatus disclosed therein.